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MCP23018/MCP23S18
16-Bit I/O Expander with Open-Drain Outputs
Features
* 16-bit remote bidirectional I/O port: - I/O pins default to input * Open-drain outputs: - 5.5V tolerant - 25 mA sink capable (per pin) - 400 mA total * High-speed I2CTM interface: (MCP23018) - 100 kHz - 400 kHz - 3.4 MHz * High-speed SPI interface: (MCP23S18) - 10 MHz: 2.7V VDD 5.5V * Single hardware address pin: (MCP23018) - Voltage input to allow up to eight devices on the bus * Configurable interrupt output pins: - Configurable as active-high, active-low or open-drain * Configurable interrupt source: - Interrupt-on-change from configured defaults or pin change * Polarity inversion register to configure the polarity of the input port data * External reset input * Low standby current: - 1 A (-40C TA +85C) - 6 A (+85C TA +125C) * Operating voltage: - 1.8V to 5.5V
Packages
28-pin PDIP (300 mil) 28-pin SOIC (300 mil) 24-pin SSOP (MCP23018 only) 24-pin QFN (4x4 [mm])
Block Diagram
MCP23S18 CS SCK SI SO SPI MCP23018 SCL SDA I2C Serializer/ Deserializer GPIO ADDR RESET INTA INTB Multi-bit Decode Open-drain GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0
Control 16
Interrupt Logic 8 GPIO Configuration/ Control Registers
(c) 2008 Microchip Technology Inc.
DS22103A-page 1
MCP23018/MCP23S18
Package Types:
MCP23018 PDIP/SOIC VSS NC GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD SCL SDA NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB NC RESET ADDR VSS GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD SCL SDA 1 2 3 4 5 6 7 8 9 10 11 12 SSOP 24 23 22 21 20 19 18 17 16 15 14 13 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET ADDR
QFN GPB0 24 GPB1 1 GPB2 2 GPB3 3 GPB4 4 GPB5 5 GPB6 6 SDA 10 ADDR 11 GPB7 7 VDD 8 SCL 9 EP 25 GPA7 22 GPA6 21 GPA5 20 GPA4 19 VSS 23
18 GPA3 17 GPA2 16 GPA1 15 GPA0 14 INTA 13 INTB
RESET 12
DS22103A-page 2
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
Package Types:
MCP23S18 PDIP/SOIC GPB0 24 VSS NC GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD CS SCK SI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB NC RESET SO VSS 23 VDD 8 QFN * GPA7 22 GPA6 21 GPA5 20 GPA4 19
GPB1 1 GPB2 2 GPB3 3 GPB4 4 GPB5 5 GPB6 6 SCK 10 GPB7 7 CS 9 SI 11 EP 25
18 GPA3 17 GPA2 16 GPA1 15 GPA0 14 INTA * 13 RESET
* INTB is not bonded out. Can be controlled in IOCON.MIRROR
(c) 2008 Microchip Technology Inc.
SO 12
DS22103A-page 3
MCP23018/MCP23S18
1.0 DEVICE OVERVIEW
The MCP23X18 device provides 16-bit, general purpose parallel I/O expansion for I2C bus or SPI applications. The two devices differ only in the serial interface. * MCP23018 - I2C interface * MCP23S18 - SPI interface The MCP23X18 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system master. The 16-bit I/O port functionally consists of two (2) 8-bit ports (PORTA and PORTB). The MCP23X18 can be configured to operate in 8-bit mode or 16-bit mode via IOCON.BANK. There are two interrupt pins, INTA and INTB which can be associated with their respective ports, or can be logically OR'ed together so both pins will activate if either port causes an interrupt. The interrupt output can be configured to activate under two conditions (mutually exclusive): 1. When any input state differs from its corresponding input port register state. This is used to indicate to the system master that an input state has changed. When an input state differs from a preconfigured register value (DEFVAL register).
2.
The Interrupt Capture register captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt. The Power-on Reset (POR) sets the registers to their default values and initializes the device state machine. The hardware address pin is used to determine the device address.
DS22103A-page 4
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.1 Pin Descriptions
I2C PINOUT DESCRIPTION (MCP23018)
24L QFN 24 1 2 3 4 5 6 7 8 23 9 10 11 12 13 14 15 16 17 18 19 20 21 22 -- 25 24L Pin SSOP Type 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -- -- I/O I/O I/O I/O I/O I/O I/O I/O P P I I/O I I O O I/O I/O I/O I/O I/O I/O I/O I/O Standard Function Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Power Ground Serial clock input Serial data I/O Hardware address pin allows up to 8 slave devices on the bus Hardware reset Interrupt output for port B. Can be configured as active high, active low, or open drain. Interrupt output for port A. Can be configured as active high, active low, or open drain. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Not connected Exposed Thermal Pad (EP). Do not electrically connect, or connect to VSS.
TABLE 1-1:
Pin Name GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS SCL SDA ADDR RESET INTB INTA GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 NC EP 28L PDIP/ SOIC 3 4 5 6 7 8 9 10 11 1 12 13 15 16 18 19 20 21 22 23 24 25 26 27 2, 14, 17, 28 --
(c) 2008 Microchip Technology Inc.
DS22103A-page 5
MCP23018/MCP23S18
TABLE 1-2:
Pin Name GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 VDD VSS CS SCK SI SO RESET INTB INTA GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 NC EP 28L PDIP/ SOIC 3 4 5 6 7 8 9 10 11 1 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 2, 17, 28 --
SPI PINOUT DESCRIPTION (MCP23S18)
24L QFN 24 1 2 3 4 5 6 7 8 23 9 10 11 12 13 -- 14 15 16 17 18 19 20 21 22 -- 25 -- Pin Type I/O I/O I/O I/O I/O I/O I/O I/O P P I I I O I O O I/O I/O I/O I/O I/O I/O I/O I/O Standard Function Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Power (high current capable) Ground (high current capable) Chip select Serial clock input Serial data input Serial data out Hardware reset (must be externally biased) Interrupt output for port B. Can be configured as active high, active low, or open drain. Interrupt output for port A. Can be configured as active high, active low, or open drain. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled for interrupt on change, and/or internal pull-up resistor. Not connected Exposed Thermal Pad (EP). Do not electrically connect, or connect to VSS.
DS22103A-page 6
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.2 Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until VDD has reached a high enough voltage to deactivate the POR circuit (i.e., release the device from reset). The maximum VDD rise time is specified in the electrical specification section. When the device exits the POR condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation. modes explained here relate to the device's internal address pointer and whether or not it is incremented after each byte is clocked on the serial interface. Byte Mode disables automatic address pointer incrementing. When operating in Byte Mode, the MCP23X18 does not increment its internal address counter after each byte during the data transfer. This gives the ability to continually access the same address by providing extra clocks (without additional control bytes). This is useful for polling the GPIO register for data changes or for continually writing to the output latches. A special mode (Byte Mode with IOCON.BANK = 0) causes the address pointer to toggle between associated A/B register pairs. For example, if the BANK bit is cleared and the address pointer is initially set to address 12h (GPIOA) or 13h (GPIOB), the pointer will toggle between GPIOA and GPIOB. Note, the address pointer can initially point to either address in the register pair. Sequential Mode enables automatic address pointer incrementing. When operating in Sequential Mode, the MCP23X18 increments its address counter after each byte during the data transfer. The address pointer automatically rolls over to address 00h after accessing the last register. These two modes are not to be confused with single writes/reads and continuous writes/reads which are serial protocol sequences. For example, the device may be configured for Byte Mode and the master may perform a continuous read. In this case, the MCP23X18 would not increment the address pointer and would repeatedly drive data from the same location.
1.3
Serial Interface
This block handles the functionality of the I2C (MCP23018) or SPI (MCP23S18) interface protocol. The MCP23X18 contains twenty two (22) individual registers (eleven [11] register pairs) which can be addressed through the Serial Interface block (Table 11).
TABLE 1-1:
REGISTER ADDRESSES
Address Address Access to: IOCON.BANK = 1 IOCON.BANK = 0 00h 10h 01h 11h 02h 12h 03h 13h 04h 14h 05h 15h 06h 16h 07h 17h 08h 18h 09h 19h 0Ah 1Ah 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h IODIRA IODIRB IPOLA IPOLB GPINTENA GPINTENB DEFVALA DEFVALB INTCONA INTCONB IOCON IOCON GPPUA GPPUB INTFA INTFB INTCAPA INTCAPB GPIOA GPIOB OLATA OLATB
1.3.2 1.3.2.1
I2C INTERFACE I2C Write Operation
The I2C write operation includes the control byte and register address sequence, as shown in the bottom of Figure 1-1. This sequence is followed by eight bits of data from the master and an Acknowledge (ACK) from the MCP23018. The operation is ended with a stop (P) or restart (SR) condition being generated by the master. Data is written to the MCP23018 after every byte transfer. If a stop or restart condition is generated during a data transfer, the data will not be written to the MCP23018. Both "byte mode" and "sequential mode" are supported by the MCP23018. If sequential mode is enabled (default), the MCP23018 increments its address counter after each ACK during the data transfer.
1.3.1
BYTE MODE AND SEQUENTIAL MODE
The MCP23X18 has the ability to operate in "Byte Mode" or "Sequential Mode" (IOCON.SEQOP). Byte mode and sequential mode are not to be confused with I2C byte operations and sequential operations. The
(c) 2008 Microchip Technology Inc.
DS22103A-page 7
MCP23018/MCP23S18
1.3.2.2
2
I2C Read Operation
1.3.3 1.3.3.1
SPI INTERFACE SPI Write Operation
I C read operations include the control byte sequence, as shown in the bottom of Figure 1-1. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit equal to a logic one (R/W = 1). The MCP23018 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition.
The SPI write operation is started by lowering CS. The write command (slave address with R/W bit cleared) is then clocked into the device. The opcode is followed by an address and at least one data byte.
1.3.3.2
SPI Read Operation
1.3.2.3
I2C Sequential Write/Read
For sequential operations (Write or Read), instead of transmitting a Stop or Restart condition after the data transfer, the master clocks the next byte pointed to by the address pointer (see Section 1.3.1 "Byte Mode and Sequential Mode" for details regarding sequential operation control). The sequence ends with the master sending a Stop or Restart condition. The MCP23018 address pointer will roll over to address zero after reaching the last register address. Refer to Figure 1-1.
The SPI read operation is started by lowering CS. The SPI read command (slave address with R/W bit set) is then clocked into the device. The opcode is followed by an address, with at least one data byte being clocked out of the device.
1.3.3.3
SPI Sequential Write/Read
For sequential operations, instead of deselecting the device by raising CS, the master clocks the next byte pointed to by the address pointer. (see Section 1.3.1 "Byte Mode and Sequential Mode" for details regarding sequential operation control). The sequence ends by the raising of CS. The MCP23S18 address pointer will roll over to address zero after reaching the last register address.
DS22103A-page 8
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
FIGURE 1-1:
S - Start SR - Restart P - Stop w - Write SR OP R DOUT .... DOUT P S OP W ADDR DIN .... DIN P
MCP23018 I2CTM DEVICE PROTOCOL
R - Read OP ADDR DOUT DIN - Device opcode - Device address - Data out from MCP23018 - Data in to MCP23018 SR P OP W ADDR .... DIN P
S
OP
R
DOUT
....
DOUT
P
SR
OP
R
DOUT
....
DOUT
P
SR
OP P
W
ADDR
DIN
....
DIN
P
Byte and Sequential Write Byte Sequential S S OP OP W ADDR DIN DIN .... P DIN P
W ADDR
Byte and Sequential Read Byte S Sequential S
OP W ADDR W ADDR SR OP R DOUT DOUT P
OP
SR
OP
R
....
DOUT
P
(c) 2008 Microchip Technology Inc.
DS22103A-page 9
MCP23018/MCP23S18
1.4 Multi-bit Address Decoder
The ADDR pin is used to set the slave address of the MCP23018 (I2C only) to allow up to eight devices on the bus using only a single pin. Typically, this would require three pins. The multi-bit Address Decoder employs a basic FLASH ADC architecture (Figure 1-4). The seven comparators generate 8 unique values based on the analog input. This value is converted to a 3-bit code which corresponds to the address bits (A2, A1, A0) in the serial OPCODE. Sequence timings): 1. of Operation (see Figure 1-5 for 2. 3. The 3-bit address is latched after tADDRLAT. The module powers down after the first rising edge of the serial clock is detected (tADDIS).
Once the address bits are latched, the device will keep the slave address until a POR or reset condition occurs.
1.4.1
CALCULATING VOLTAGE ON ADDR
When calculating the required voltage on the ADDR pin (V2), the set point should be the mid-point of the LSb of the ADC. The examples in Figure 1-2 and Figure 1-3 show how to determine the mid point voltage (V2) and the range of voltages based on a voltage divider circuit. The maximum tolerance is 20%, however, it is recommended to use 5% tolerance worst case (10% total tolerance).
Upon power up (after VDD stabilizes) the module becomes active after time tADEN. Note, the analog value on the ADDR pin must be stable before this point to ensure accurate address assignment.
FIGURE 1-2:
VOLTAGE DIVIDER EXAMPLE
VDD VDD
ADDR
MCP23018 A0
R1
A1 A2
V2
R2
VSS
VSS
DS22103A-page 10
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
FIGURE 1-3: VOLTAGE AND CODE EXAMPLE
Assume: n = A2, A1, A0 in opcode ratio = R2/(R1+R2) V2 = voltage on ADDR pin V2(min) = V2 - (VDD/8) x %tolerance V2(max) = V2 + (VDD/8) x %tolerance
n 0 1 2 3 4 5 6 7
R2=2n+1 1 3 5 7 9 11 13 15
10% Tolerance (total) VDD= 1.8 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 0.113 15 0.0625 0.00 0.14 13 0.1875 0.32 0.36 0.338 11 0.3125 0.54 0.59 0.563 0.788 9 0.4375 0.77 0.81 7 0.5625 0.99 1.04 1.013 1.238 5 0.6875 1.22 1.26 3 0.8125 1.44 1.49 1.463 1 0.9375 1.67 1.80 1.688
n 0 1 2 3 4 5 6 7
R2=2n+1 1 3 5 7 9 11 13 15
10% Tolerance (total) VDD= 2.7 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 0.169 15 0.0625 0.00 0.19 13 0.1875 0.48 0.53 0.506 0.844 11 0.3125 0.82 0.87 9 0.4375 1.16 1.20 1.181 7 0.5625 1.50 1.54 1.519 1.856 5 0.6875 1.83 1.88 3 0.8125 2.17 2.22 2.194 2.531 1 0.9375 2.51 2.70
n 0 1 2 3 4 5 6 7
R2=2n+1 1 3 5 7 9 11 13 15
VDD= 3.3 R1=16-R2 R2/(R1+R2) V2 15 0.0625 0.206 13 0.1875 0.619 1.031 11 0.3125 9 0.4375 1.444 1.856 7 0.5625 5 0.6875 2.269 2.681 3 0.8125 1 0.9375 3.094
10% Tolerance (total) V2(min) V2(max) 0.00 0.23 0.60 0.64 1.01 1.05 1.42 1.47 1.83 1.88 2.25 2.29 2.66 2.70 3.07 3.30
n 0 1 2 3 4 5 6 7
R2=2n+1 1 3 5 7 9 11 13 15
VDD= 5.5 10% Tolerance (total) R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max) 15 0.0625 0.00 0.37 0.344 1.031 13 0.1875 1.01 1.05 11 0.3125 1.70 1.74 1.719 9 0.4375 2.38 2.43 2.406 3.094 7 0.5625 3.07 3.12 5 0.6875 3.76 3.80 3.781 4.469 3 0.8125 4.45 4.49 1 0.9375 5.13 5.50 5.156
(c) 2008 Microchip Technology Inc.
DS22103A-page 11
MCP23018/MCP23S18
FIGURE 1-4: FLASH ADC BLOCK DIAGRAM
VDD analog_in
addr_out[6] adc_en addr_out[5] adc_en addr_out[4] adc_en addr_out[3] adc_en addr_out[2] adc_en addr_out[1] adc_en addr_out[0] adc_en i2c_clk '0' adc_en
d en
q
addr[6:0]
i2c_addr[2:0]
reset set d q adc_en
adc_en gnd
DS22103A-page 12
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
FIGURE 1-5: HARDWARE ADDRESS DECODE TIMING
tADEN VDD
tADDRLAT adc_en
i2c_addr[2:0] tADDIS
i2c_clk
1.4.2
ADDRESSING I2C DEVICES (MCP23018)
FIGURE 1-6:
I2CTM CONTROL BYTE FORMAT
Control Byte
The MCP23018 is a slave I2C device that supports 7bit slave addressing, with the read/write bit filling out the control byte. The slave address contains four fixed bits and three user-defined hardware address bits (pins A2, A1, and A0). Figure 1-6 shows the control byte format.
S
0
1
0
0
A2 A1 A0 R/W ACK
Slave Address Start bit R/W = 0 = write R/W = 1 = read R/W bit ACK bit
1.4.3
ADDRESSING SPI DEVICES (MCP23S18)
The MCP23S18 is a slave SPI device. The slave address contains seven fixed bits(no address bits) with the read/write bit filling out the control byte. Figure 1-7 shows the control byte format.
FIGURE 1-7:
CS
SPI CONTROL BYTE FORMAT
Control Byte 0 1 0 0 0 0 0 R/W
Slave Address R/W bit R/W = 0 = write R/W = 1 = read
(c) 2008 Microchip Technology Inc.
DS22103A-page 13
MCP23018/MCP23S18
FIGURE 1-8:
S 0 1 0
I2CTM ADDRESSING REGISTERS
0 A2 A1 A0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
R/W = 0 Device Opcode Register Address
The ACKs are provided by the MCP23X18.
FIGURE 1-9:
SPI ADDRESSING REGISTERS
CS 0 1 0 0 0 0 0 R/W A7 A6 A5 A4 A3 A2 A1 A0
Device Opcode
Register Address
DS22103A-page 14
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.5 GPIO Port
The GPIO module is a general purpose 16-bit wide bidirectional port which is functionally split into two (2) 8-bit wide ports. The outputs are open-drain. The GPIO module contains the data ports (GPIOn), internal pull up resistors and the Output Latches (OLATn). The pull up resistors are individually configured and can be enabled when the pin is cofigured as an input or output. Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port. Writing to the GPIOn register actually causes a write to the latches (OLATn). Writing to the OLATn register forces the associated output drivers to drive to the level in OLATn. Pins configured as inputs turn off the associated output driver and put it in high-impedance.
TABLE 1-2:
Register Name IODIRA IPOLA GPINTENA GPPUA GPIOA OLATA IODIRB IPOLB GPINTENB GPPUB GPIOB OLATB
SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1)
Address (hex) 00 01 02 06 09 0A 10 11 12 16 19 1A bit 7 IO7 IP7 GPINT7 PU7 GP7 OL7 IO7 IP7 GPINT7 PU7 GP7 OL7 bit 6 IO6 IP6 GPINT6 PU6 GP6 OL6 IO6 IP6 GPINT6 PU6 GP6 OL6 bit 5 IO5 IP5 GPINT5 PU5 GP5 OL5 IO5 IP5 GPINT5 PU5 GP5 OL5 bit 4 IO4 IP4 GPINT4 PU4 GP4 OL4 IO4 IP4 GPINT4 PU4 GP4 OL4 bit 3 IO3 IP3 GPINT3 PU3 GP3 OL3 IO3 IP3 GPINT3 PU3 GP3 OL3 bit 2 IO2 IP2 GPINT2 PU2 GP2 OL2 IO2 IP2 GPINT2 PU2 GP2 OL2 bit 1 IO1 IP1 GPINT1 PU1 GP1 OL1 IO1 IP1 GPINT1 PU1 GP1 OL1 bit 0 IO0 IP0 GPINT0 PU0 GP0 OL0 IO0 IP0 GPINT0 PU0 GP0 OL0 POR/RST value 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
TABLE 1-3:
Register Name IODIRA IODIRB IPOLA IPOLB GPINTENA GPINTENB GPPUA GPPUB GPIOA GPIOB OLATA OLATB
SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0)
Address (hex) 00 01 02 03 04 05 0C 0D 12 13 14 15 bit 7 IO7 IO7 IP7 IP7 GPINT7 GPINT7 PU7 PU7 GP7 GP7 OL7 OL7 bit 6 IO6 IO6 IP6 IP6 GPINT6 GPINT6 PU6 PU6 GP6 GP6 OL6 OL6 bit 5 IO5 IO5 IP5 IP5 GPINT5 GPINT5 PU5 PU5 GP5 GP5 OL5 OL5 bit 4 IO4 IO4 IP4 IP4 GPINT4 GPINT4 PU4 PU4 GP4 GP4 OL4 OL4 bit 3 IO3 IO3 IP3 IP3 GPINT3 GPINT3 PU3 PU3 GP3 GP3 OL3 OL3 bit 2 IO2 IO2 IP2 IP2 GPINT2 GPINT2 PU2 PU2 GP2 GP2 OL2 OL2 bit 1 IO1 IO1 IP1 IP1 GPINT1 GPINT1 PU1 PU1 GP1 GP1 OL1 OL1 bit 0 IO0 IO0 IP0 IP0 GPINT0 GPINT0 PU0 PU0 GP0 GP0 OL0 OL0 POR/RST value 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
(c) 2008 Microchip Technology Inc.
DS22103A-page 15
MCP23018/MCP23S18
1.6 Configuration and Control Registers
with Port A and ten (10) are associated with Port B. One register (IOCON) is shared between the two ports. The Port A registers are identical to the Port B registers, therefore, they will be referred to without differentiating between the port designation (i.e., they will not have the "A" or "B" designator assigned) in the register tables.
There are twenty two (22) registers associated with the MCP23X18 as shown in Table 1-4 and Table 1-5. The two tables show the register mapping with the two BANK bit values. Ten (10) registers are associated
TABLE 1-4:
Register Name IODIRA IPOLA GPINTENA DEFVALA INTCONA IOCON GPPUA INTFA INTCAPA GPIOA OLATA IODIRB IPOLB GPINTENB DEFVALB INTCONB IOCON GPPUB INTFB INTCAPB GPIOB OLATB
CONTROL REGISTER SUMMARY (IOCON.BANK = 1)
Address (hex) 00 01 02 03 04 05 06 07 08 09 0A 10 11 12 13 14 15 16 17 18 19 1A bit 7 IO7 IP7 GPINT7 DEF7 IOC7 BANK PU7 INT7 ICP7 GP7 OL7 IO7 IP7 GPINT7 DEF7 IOC7 BANK PU7 INT7 ICP7 GP7 OL7 bit 6 IO6 IP6 GPINT6 DEF6 IOC6 MIRROR PU6 INT6 ICP6 GP6 OL6 IO6 IP6 GPINT6 DEF6 IOC6 MIRROR PU6 INT6 ICP6 GP6 OL6 bit 5 IO5 IP5 GPINT5 DEF5 IOC5 SEQOP PU5 INT5 ICP5 GP5 OL5 IO5 IP5 GPINT5 DEF5 IOC5 SEQOP PU5 INT5 ICP5 GP5 OL5 bit 4 IO4 IP4 GPINT4 DEF4 IOC4 -- PU4 INT4 ICP4 GP4 OL4 IO4 IP4 GPINT4 DEF4 IOC4 -- PU4 INT4 ICP4 GP4 OL4 bit 3 IO3 IP3 GPINT3 DEF3 IOC3 -- PU3 INT3 ICP3 GP3 OL3 IO3 IP3 GPINT3 DEF3 IOC3 -- PU3 INT3 ICP3 GP3 OL3 bit 2 IO2 IP2 GPINT2 DEF2 IOC2 ODR PU2 INT2 ICP2 GP2 OL2 IO2 IP2 GPINT2 DEF2 IOC2 ODR PU2 INT2 ICP2 GP2 OL2 bit 1 IO1 IP1 GPINT1 DEF1 IOC1 INTPOL PU1 INT1 ICP1 GP1 OL1 IO1 IP1 GPINT1 DEF1 IOC1 INTPOL PU1 INT1 ICP1 GP1 OL1 bit 0 IO0 IP0 GPINT0 DEF0 IOC0 INTCC PU0 INTO ICP0 GP0 OL0 IO0 IP0 GPINT0 DEF0 IOC0 INTCC PU0 INTO ICP0 GP0 OL0 POR/RST value 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DS22103A-page 16
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
TABLE 1-5:
Register Name IODIRA IODIRB IPOLA IPOLB GPINTENA GPINTENB DEFVALA DEFVALB INTCONA INTCONB IOCON IOCON GPPUA GPPUB INTFA INTFB INTCAPA INTCAPB GPIOA GPIOB OLATA OLATB
CONTROL REGISTER SUMMARY (IOCON.BANK = 0)
Address (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 bit 7 IO7 IO7 IP7 IP7 GPINT7 GPINT7 DEF7 DEF7 IOC7 IOC7 BANK BANK PU7 PU7 INT7 INT7 ICP7 ICP7 GP7 GP7 OL7 OL7 bit 6 IO6 IO6 IP6 IP6 GPINT6 GPINT6 DEF6 DEF6 IOC6 IOC6 MIRROR MIRROR PU6 PU6 INT6 INT6 ICP6 ICP6 GP6 GP6 OL6 OL6 bit 5 IO5 IO5 IP5 IP5 GPINT5 GPINT5 DEF5 DEF5 IOC5 IOC5 SEQOP SEQOP PU5 PU5 INT5 INT5 ICP5 ICP5 GP5 GP5 OL5 OL5 bit 4 IO4 IO4 IP4 IP4 GPINT4 GPINT4 DEF4 DEF4 IOC4 IOC4 -- -- PU4 PU4 INT4 INT4 ICP4 ICP4 GP4 GP4 OL4 OL4 bit 3 IO3 IO3 IP3 IP3 GPINT3 GPINT3 DEF3 DEF3 IOC3 IOC3 -- -- PU3 PU3 INT3 INT3 ICP3 ICP3 GP3 GP3 OL3 OL3 bit 2 IO2 IO2 IP2 IP2 GPINT2 GPINT2 DEF2 DEF2 IOC2 IOC2 ODR ODR PU2 PU2 INT2 INT2 ICP2 ICP2 GP2 GP2 OL2 OL2 bit 1 IO1 IO1 IP1 IP1 GPINT1 GPINT1 DEF1 DEF1 IOC1 IOC1 INTPOL INTPOL PU1 PU1 INT1 INT1 ICP1 ICP1 GP1 GP1 OL1 OL1 bit 0 IO0 IO0 IP0 IP0 GPINT0 GPINT0 DEF0 DEF0 IOC0 IOC0 INTCC INTCC PU0 PU0 INTO INTO ICP0 ICP0 GP0 GP0 OL0 OL0 POR/RST value 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
(c) 2008 Microchip Technology Inc.
DS22103A-page 17
MCP23018/MCP23S18
1.6.1 I/O DIRECTION REGISTER
Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output.
REGISTER 1-3:
R/W-1 IO7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
IODIR - I/O DIRECTION REGISTER
R/W-1 IO6 R/W-1 IO5 R/W-1 IO4 R/W-1 IO3 R/W-1 IO2 R/W-1 IO1 R/W-1 IO0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IO7:IO0: Controls the direction of data I/O <7:0> 1 = Pin is configured as an input. 0 = Pin is configured as an output.
DS22103A-page 18
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.6.2 INPUT POLARITY REGISTER
This register allows the user to configure the polarity on the corresponding GPIO port bits. If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin.
REGISTER 1-4:
R/W-0 IP7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
IPOL - INPUT POLARITY PORT REGISTER
R/W-0 IP6 R/W-0 IP5 R/W-0 IP4 R/W-0 IP3 R/W-0 IP2 R/W-0 IP1 R/W-0 IP0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IP7:IP0: Controls the polarity inversion of the input pins <7:0> 1 = GPIO register bit will reflect the opposite logic state of the input pin. 0 = GPIO register bit will reflect the same logic state of the input pin.
(c) 2008 Microchip Technology Inc.
DS22103A-page 19
MCP23018/MCP23S18
1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER
The GPINTEN register controls the interrupt-onchange feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change.
REGISTER 1-5:
R/W-0 GPINT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
GPINTEN - INTERRUPT-ON-CHANGE PINS
R/W-0 GPINT6 R/W-0 GPINT5 R/W-0 GPINT4 R/W-0 GPINT3 R/W-0 GPINT2 R/W-0 GPINT1 R/W-0 GPINT0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GPINT7:GPINT0: General purpose I/O interrupt-on-change pins <7:0> 1 = Enable GPIO input pin for interrupt-on-change event 0 = Disable GPIO input pin for interrupt-on-change event.
DS22103A-page 20
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.6.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur.
REGISTER 1-6:
R/W-0 DEF7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
DEFVAL - DEFAULT VALUE REGISTER
R/W-0 DEF6 R/W-0 DEF5 R/W-0 DEF4 R/W-0 DEF3 R/W-0 DEF2 R/W-0 DEF1 R/W-0 DEF0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DEF7:DEF0: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>. Refer to INTCON. If the associated pin level is the opposite from the register bit, an interrupt occurs. Refer to INTCON and GPINTEN.
(c) 2008 Microchip Technology Inc.
DS22103A-page 21
MCP23018/MCP23S18
1.6.5 INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value.
REGISTER 1-7:
R/W-0 IOC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
INTCON - INTERRUPT-ON-CHANGE CONTROL REGISTER
R/W-0 IOC6 R/W-0 IOC5 R/W-0 IOC4 R/W-0 IOC3 R/W-0 IOC2 R/W-0 IOC1 R/W-0 IOC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IOC7:IOC0: Controls how the associated pin value is compared for interrupt-on-change <7:0>. 1 = Pin value is compared against the associated bit is DEFVAL register 0 = Pin value is compared against the previous pin value. Refer to INTCON and GPINTEN.
DS22103A-page 22
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.6.6 CONFIGURATION REGISTER
contains several bits for The IOCON register configuring the device: Note: The INTB pin is not bonded out on the MCP23S18 (SPI) device in the 24-lead QFN package. The MIRROR bit must be configured to a "1" in order for interrupts to be detected on PORTB.
The BANK bit changes how the registers are mapped (see Table 1-4 and Table 1-5 for more details). * If BANK = 1, the registers associated with each port are segregated. Registers associated with PORTA are are mapped from address 00h - 0Ah and registers associated with PORTB are mapped from Address 10h - 1Ah * If BANK = 0, the A/B registers are paired. For example, IODIRA is mapped to address 00h and IODIRB is mapped to the next address (address 01h). The mapping for all registers is from 00h 15h It is important to take care when changing the BANK bit as the address mapping changes after the byte is clocked into the device. The address pointer may point to an invalid location after the bit is modified. For example, if the device is configured to automatically increment its internal address pointer the following scenario would occur: * BANK = 0 * Write 80h to 0Ah (IOCON) to set the BANK bit * After the write completes the internal address now points to 0Bh which is an invalid address when the BANK bit is set For this reason, it is advised to only perform byte writes to this register when changing the BANK bit.
The MIRROR bit controls how the INTA and INTB pins function with respect to each other. * When MIRROR = 1, the INTn pins are functionally OR'ed so that an interrupt on either port will cause both pins to activate * When MIRROR = 0, the INT pins are separated. Interrupt conditions on a port will cause its respective INT pin to activate The Sequential Operation (SEQOP) controls the incrementing function of the address pointer. If the address pointer is disabled, the address pointer does not automatically increment after each byte is clocked during a serial transfer. This feature is useful when it is desired to continuously poll (read) or modify (write) a register. The Open-Drain (ODR) control bit enables/disables the INT pin for open-drain configuration. The Interrupt Polarity (INTPOL) sets the polarity of the INT pin. This bit is functional only when the ODR bit is cleared, configuring the INT pin as active push-pull. The Interrupt Clearing Control (INTCC) configures how interrupts are cleared. When set (INTCC = 1), the interrupt is cleared when the INTCAP register is read. When cleared (INTCC = 0), the interrupt is cleared when the GPIO register is read. The interrupt can only be cleared when the interrupt condition is inactive. Refer to Section 1.7.5 "Clearing Interrupts" for details.
(c) 2008 Microchip Technology Inc.
DS22103A-page 23
MCP23018/MCP23S18
REGISTER 1-8:
R/W-0 BANK bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IOCON - I/O EXPANDER CONFIGURATION REGISTER
R/W-0 MIRROR R/W-0 SEQOP U-0 U-0 R/W-0 ODR R/W-0 INTPOL R/W-0 INTCC bit 0
BANK: Controls how the registers are addressed (see Figure 1-4 and Figure 1-5) 1 = The registers associated with each port are separated into different banks 0 = The registers are in the same bank (addresses are sequential) MIRROR: INT pins mirror bit 1 = The INT pins are internally connected in a wired OR configuration 0 = The INT pins are not connected. INTA is associated with Port A and INTB is associated with Port B SEQOP: Sequential Operation mode bit. 1 = Sequential operation disabled, address pointer does not increment. 0 = Sequential operation enabled, address pointer increments. Unimplemented: Reads as 0 Unimplemented: Reads as 0 ODR: Configures the INT pin as an open-drain output. 1 = Open-drain output (overrides the INTPOL bit). 0 = Active driver output (INTPOL bit sets the polarity). INTPOL: Sets the polarity of the INT output pin. 1 = Active-high. 0 = Active-low. INTCC: Interrupt Clearing Control 1 = Reading INTCAP register clears the interrupt 0 = Reading GPIO register clears the interrupt
bit 6
bit 5
bit 4 bit 3 bit 2
bit 1
bit 0
DS22103A-page 24
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.6.7 PULL-UP RESISTOR CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the port pins. If a bit is set the corresponding port pin is internally pulled up with an internal resistor.
REGISTER 1-9:
R/W-0 PU7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
GPPU - GPIO PULL-UP RESISTOR REGISTER
R/W-0 PU6 R/W-0 PU5 R/W-0 PU4 R/W-0 PU3 R/W-0 PU2 R/W-0 PU1 R/W-0 PU0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PU7:PU0: Controls the internal pull-up resistors on each pin (when configured as an input or output) <7:0>. 1 = Pull-up enabled. 0 = Pull-up disabled.
FIGURE 1-10:
TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS
GPIO Pin Internal Pull-up Current vs VDD
400 350 300 IPU (A) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 VDD (V) 4 4.5 5 5.5
T = +85C T = +125C T = +25C T = -40C
(c) 2008 Microchip Technology Inc.
DS22103A-page 25
MCP23018/MCP23S18
1.6.8 INTERRUPT FLAG REGISTER
The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A `set' bit indicates that the associated pin caused the interrupt. This register is `read only'. Writes to this register will be ignored.
REGISTER 1-10:
R-0 INT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
INTF - INTERRUPT FLAG REGISTER
R-0 INT6 R-0 INT5 R-0 INT4 R-0 INT3 R-0 INT2 R-0 INT1 R-0 INT0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
INT7:INT0: Reflects the interrupt condition on the port. Will reflect the change only if interrupts are enabled (GPINTEN) <7:0>. 1 = Pin caused interrupt. 0 = Interrupt not pending.
DS22103A-page 26
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.6.9 INTERRUPT CAPTURE REGISTER
The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is `read only' and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO.
REGISTER 1-11:
R-x ICP7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
INTCAP - INTERRUPT CAPTURED VALUE FOR PORT REGISTER
R-x ICP6 R-x ICP5 R-x ICP4 R-x ICP3 R-x ICP2 R-x ICP1 R-x ICP0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ICP7:ICP0: Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0>. 1 = Logic-high. 0 = Logic-low.
(c) 2008 Microchip Technology Inc.
DS22103A-page 27
MCP23018/MCP23S18
1.6.10 PORT REGISTER
The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register.
REGISTER 1-12:
R/W-0 GP7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
GPIO - GENERAL PURPOSE I/O PORT REGISTER
R/W-0 GP6 R/W-0 GP5 R/W-0 GP4 R/W-0 GP3 R/W-0 GP2 R/W-0 GP1 R/W-0 GP0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GP7:GP0: Reflects the logic level on the pins <7:0>. 1 = Logic-high. 0 = Logic-low.
DS22103A-page 28
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.6.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs.
REGISTER 1-13:
R/W-0 OL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
OLAT - OUTPUT LATCH REGISTER 0
R/W-0 OL6 R/W-0 OL5 R/W-0 OL4 R/W-0 OL3 R/W-0 OL2 R/W-0 OL1 R/W-0 OL0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OL7:OL0: Reflects the logic level on the output latch <7:0>. 1 = Logic-high. 0 = Logic-low.
(c) 2008 Microchip Technology Inc.
DS22103A-page 29
MCP23018/MCP23S18
1.7 Interrupt Logic
1.7.2 IOC FROM PIN CHANGE
If enabled, the MCP23X18 activates the INTn interrupt output when one of the port pins changes state or when a pin does not match the pre-configured default. Each pin is individually configurable as follows: * Enable/disable interrupt via GPINTEN * Can interrupt on either pin change or change from default as configured in DEFVAL Both conditions are referred to as Interrupt on Change (IOC). The Interrupt Control (INT) Module uses the following registers/bits: * IOCON.MIRROR - controls if the two interrupt pins mirror each other. * GPINTEN - Interrupt enable register * INTCON - Controls the source for the IOC * DEFVAL - Contains the register default for IOC operation If enabled, the MCP23X18 will generate an interrupt if a mismatch condition exists between the current port value and the previous port value. Only IOC enabled pins will be compared. See GPINTEN and INTCON registers.
1.7.3
IOC FROM REGISTER DEFAULT
If enabled, the MCP23X18 will generate an interrupt if a mismatch occurs between the DEFVAL register and the port. Only IOC enabled pins will be compared. See GPINTEN, INTCON, and DEFVAL registers.
1.7.4
INTERRUPT OPERATION
The INTn interrupt output can be configured as "active low", "active high", or "open drain" via the IOCON register. Only those pins that are configured as an input (IODIR register) with interrupt-on-change (IOC) enabled (GPINTEN register) can cause an interrupt. Pins defined as an output have no effect on the interrupt output pin. Input change activity on a port input pin that is enabled for IOC will generate an internal device interrupt and the device will capture the value of the port and copy it into INTCAP. The first interrupt event will cause the port contents to be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of INTCAP or GPIO.
1.7.1
INTA AND INTB
There are two interrupt pins, INTA and INTB. By default, INTA is associated with GPAn pins (Port A) and INTB is associated with GPBn pins (Port B). Each port has an independent signal which is cleared if its associated GPIO or INTCAP register is read.
1.7.1.1
Mirroring the INT pins
Additionally, the INTn pins can be configured to mirror each other so that any interrupt will cause both pins to go active. This is controlled via IOCON.MIRROR. If IOCON.MIRROR = 0, the internal signals are routed independently to the INTA and INTB pads. If IOCON.MIRROR = 1, the internal signals are OR'ed together and routed to the INTn pads. In this case, the interrupt will only be cleared if the associated GPIO or INTCAP is read (see Table 1-6).
1.7.5
CLEARING INTERRUPTS
The interrupt will remain active until the INTCAP or GPIO register is read (depending on IOCON.INTCC). Writing to these registers will not affect the interrupt. The interrupt condition will be cleared after the LSb of the data is clocked out during a Read command of GPIO or INTCAP (depending on IOCON.INTCC). Note: Assuming IOCON.INTCC = 0 (INT cleared on GPIO read): The value in INTCAP can be lost if GPIO is read before INTCAP while another IOC is pending. After reading GPIO, the interrupt will clear and then set due to the pending IOC, causing the INTCAP register to update.
TABLE 1-6:
Interrupt Condition GPIOA GPIOB GPIOA and GPIOB
INTERRUPT OPERATION (IOCON.MIRROR = 1)
Read Port N* Port A Port B Port A Port B Port A Port B Both Port A and Port B Interupt Result Clear Unchanged Unchanged Clear Unchanged Unchanged Clear
* Port n = GPIOn or INTCAPn
DS22103A-page 30
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
1.7.6 INTERRUPT CONDITIONS FIGURE 1-11:
There are two possible configurations to cause interrupts (configured via INTCON): 1. Pins configured for interrupt-on-pin-change will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs. For example, an interrupt occurs by an input changing from 1 to 0. The new initial state for the pin is a logic 0. Pins configured for interrupt-on-change from register value will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTAP or GPIO is read. GPx
INTERRUPT-ON-PINCHANGE
INT Port value is captured into INTCAP
ACTIVE Read GPIO or INTCAP
ACTIVE Port value is captured into INTCAP
2.
FIGURE 1-12:
See Figure 1-11 and Figure 1-12 for more information on interrupt operations.
INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT
DEFVAL
GP:
7 X
6 X
5 X
4 X
3 X
2 1
1 X
0 X
GP2
INT
ACTIVE
ACTIVE
Port value is captured into INTCAP
Read GPIO or INTCAP (INT clears only if interrupt condition does not exist.)
(c) 2008 Microchip Technology Inc.
DS22103A-page 31
MCP23018/MCP23S18
NOTES:
DS22103A-page 32
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
2.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings ()
Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.0V Voltage on RESET with respect to VSS ..................................................................................................... -0.3V to +14V Voltage on all other pins with respect to VSS (except VDDand GPIOA/B) ...................................... -0.6V to (VDD + 0.6V) Voltage on GPIO Pins: ................................................................................................................................. -0.6V to 5.5V Total power dissipation (Note 1)...........................................................................................................................700 mW Maximum current out of VSS pin ...........................................................................................................................400 mA Maximum current into VDD pin ..............................................................................................................................125 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any Output pin....................................................................................................25 mA Maximum output current sunk by any Output pin (VDD = 1.8V) ..............................................................................10 mA Maximum output current sourced by any Output pin ..............................................................................................25 mA Maximum output current sourced by any Output pin (VDD = 1.8V).........................................................................10 mA Note: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2008 Microchip Technology Inc.
DS22103A-page 33
MCP23018/MCP23S18
2.1 DC CHARACTERISTICS
Operating Conditions (unless otherwise indicated): 1.8V VDD 5.5V at -40C TA +125C Sym VDD VPOR Min 1.8 -- Typ( 2) -- VSS Max 5.5 -- Units V V Conditions
DC Characteristics Param No. D001 D002 Characteristic Supply Voltage VDD Start Voltage to Ensure Power-on Reset VDD Rise Rate to Ensure Power-on Reset Supply Current Standby (Idle) current Input Low-Voltage D031 CS, GPIO, SCL/SCK, SDA, SI, RESET Input High-Voltage D041 CS, SCL/SCK, SDA, SI, RESET GPIO Input Leakage Current D060 D065 D070 I/O port pins
D003
SVDD
0.05
--
--
V/ms
Design guidance only. Not tested. SCL/SCK = 1 MHz -40C TA +85C +85C TA +125C
D004 D005
IDD IDDS
-- -- --
-- -- -- --
1 1 6 0.2 VDD
mA A A V
VIL
VSS
VIH VIH IIL ILO IPU
0.8 VDD 0.8 VDD -- -- --
-- -- -- -- 220
VDD 5.5 1 1 --
V V A A A VSS VPIN VDD, VSS VPIN VDD, VDD = 5V, GP Pins = VSS Note 1 IOL = 8.5 mA, VDD = 4.5V (open-drain) IOL = 1.6 mA, VDD = 4.5V IOL = 3.0 mA, VDD = 1.8V IOL = 3.0 mA, VDD = 4.5V IOH = -3.0 mA, VDD = 4.5V IOH = -400 A, VDD = 1.8V pF pF
Output Leakage Current I/O port pins GPIO internal pull-up current Output Low-Voltage D080 GPIO INT SO, SDA SDA Output High-Voltage D090 INT, SO VOH VDD - 0.7 VDD - 0.7 Capacitive Loading Specs on Output Pins D101 D102 Note 1: 2: GPIO, SO, INT SDA CIO CB -- -- -- -- 50 400 -- -- -- -- V VOL -- -- -- -- -- -- -- -- 0.6 0.6 0.6 0.8 V V V V
This parameter is characterized, not 100% tested. Data in the Typical ("Typ") column is at 5V, +25C unless otherwise stated.
DS22103A-page 34
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
2.2 AC CHARACTERISTICS
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
VDD Pin 50 pF 135 pF
FIGURE 2-1:
1 k SCL and SDA pin MCP23018
FIGURE 2-2:
VDD RESET
RESET AND DEVICE RESET TIMER TIMING
30 31 Internal RESET
32
34 Output pin
TABLE 2-1:
RESET AND DEVICE RESET TIMER REQUIREMENTS
AC Characteristics Standard Operating Conditions (unless otherwise specified) 1.8V VDD 5.5V at -40C TA +125C. Parameter No. 30 32 31 34 Note 1: 2: Sym Characteristic Min 1 -- -- -- Typ( 2) Max -- 0 20 -- -- -- -- 1 Units s s s s Conditions VDD = 5.0V VDD = 5.0V VDD = 5.0V
TRSTL RESET Pulse Width (low) THLD TioZ Device active after reset high Output Hi-impedance from RESET Low TPOR POR at device power up
This parameter is characterized, not 100% tested. Data in the Typical ("Typ") column is at 5V, +25C, unless otherwise stated.
(c) 2008 Microchip Technology Inc.
DS22103A-page 35
MCP23018/MCP23S18
TABLE 2-2: GP AND INT PINS
AC Characteristics Standard Operating Conditions (unless otherwise specified) 1.8V VDD 5.5V at -40C TA +125C. Parameter No. 50 51 52 53 54 Note 1: 2: Sym Characteristic Min -- -- -- -- -- Typ( 2) Max -- -- 450 -- -- 500 600 -- 600 50 Units ns ns ns ns ns Note 1 Note 1 Conditions
tGPOV Serial data to output valid tINTD tGPIV Interrupt pin disable time GP input change to register valid
tGPINT IOC event to INT active tGLITCH Glitch filter on GP pins
This parameter is characterized, not 100% tested. Data in the Typical ("Typ") column is at 5V, 25C, unless otherwise stated.
FIGURE 2-3:
GPIO AND INT TIMING
SCL SDA In
D1
D0 LSb of data byte zero during a write or read command, depending 50 on parameter
GPn Output Pin 51 INT Pin INT pin active INT pin inactive 53
GPn Input Pin
52 Register Loaded
DS22103A-page 36
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
TABLE 2-3: HARDWARE ADDRESS LATCH TIMING
Standard Operating Conditions (unless otherwise specified) 1.8V VDD 5.5V at -40C TA +125C. Characteristic Time from VDD stable after POR to ADC enable Min -- -- -- Typ( 2) Max 0 50 10 -- -- -- Units s ns ns Note 1 Note 1 Note 1 Conditions AC Characteristics Parameter No. 40 41 42 Note 1: 2:
Sym tADEN
tADDRLAT Time from ADC enable to address decode and latch tADDIS Time from raising edge of serial clock to ADC disable
This parameter is characterized, not 100% tested. Data in the Typical ("Typ") column is at 5V, +25C, unless otherwise stated..
FIGURE 2-4:
HARDWARE ADDRESS LATCH TIMING
40 VDD
41 adc_en
i2c_addr[2:0] 42
SCL
(c) 2008 Microchip Technology Inc.
DS22103A-page 37
MCP23018/MCP23S18
FIGURE 2-5: I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition Note 1: Refer to Figure 2-1 for load conditions.
STOP Condition
FIGURE 2-6:
I2C BUS DATA TIMING
103 100 101 102
SCL SDA In
90
91
106
107 109
92
109
110
SDA Out Note 1: Refer to Figure 2-1 for load conditions.
DS22103A-page 38
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
TABLE 2-4: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Operating Conditions (unless otherwise indicated): 1.8V VDD 5.5V at -40C TA +125C RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF. Sym THIGH 4.0 0.6 0.06 TLOW 4.7 1.3 0.16 TR (Note 1) -- 20 + 0.1 10 TF (Note 1) -- 20 + 0.1 10 TSU:STA 4.7 0.6 0.16 THD:STA 4.0 0.6 0.16 THD:DAT 0 0 0 TSU:DAT 250 100 0.01 TSU:STO 4.0 0.6 0.16 -- -- -- -- -- -- s s s 1.8V - 5.5V 2.7V - 5.5V 4.5V - 5.5V -- -- -- -- -- -- ns ns s 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V -- -- -- 3.45 0.9 0.07 s s s 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V -- -- -- -- -- -- s s s 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V -- -- -- -- -- -- s s s 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V CB(2) CB(2) -- -- -- -- -- -- -- -- -- -- -- -- 1000 300 80 300 300 80 s s s ns ns ns ns ns ns 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V -- -- -- -- -- -- s s s 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V Min Typ Max Units Conditions I2CTM AC Characteristics Param No. 100
Characteristic Clock High Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
101
Clock Low Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
102
SDA and SCL Rise Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
103
SDA and SCL Fall Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
90
START Condition Setup Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
91
START Condition Hold Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
106
Data Input Hold Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
107
Data Input Setup Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
92
STOP Condition Setup Time: 100 kHz mode 400 kHz mode 3.4 MHz mode
Note 1: 2: 3:
This parameter is characterized, not 100% tested. CB is specified from 10 to 400 (pF). This parameter is not applicable in high-speed mode (3.4 MHz).
(c) 2008 Microchip Technology Inc.
DS22103A-page 39
MCP23018/MCP23S18
TABLE 2-4: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
Operating Conditions (unless otherwise indicated): 1.8V VDD 5.5V at -40C TA +125C RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF. Sym TAA -- -- -- TBUF (NOTE 3) 4.7 1.3 N/A CB (NOTE 2) -- -- TSP -- -- -- -- 50 10 ns ns (Note 1) (Note 1) -- -- -- -- -- -- -- -- 3.45 0.9 0.18 -- -- N/A 400 100 s s s s s s pF pF 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V 1.8V - 5.5V 1.8V - 5.5V 2.7V - 5.5V (Note 1) (Note 1) Min Typ Max Units Conditions I2CTM AC Characteristics Param No. 109
Characteristic Output Valid From Clock: 100 kHz mode 400 kHz mode 3.4 MHz mode
110
Bus Free Time: 100 kHz mode 400 kHz mode 3.4 MHz mode Bus Capacitive Loading: 100 kHz and 400 kHz 3.4 MHz Input Filter Spike Suppression: (SDA and SCL) 100 kHz and 400 kHz 3.4 MHz
Note 1: 2: 3:
This parameter is characterized, not 100% tested. CB is specified from 10 to 400 (pF). This parameter is not applicable in high-speed mode (3.4 MHz).
FIGURE 2-7:
SPI INPUT TIMING
3
CS 11 1 Mode 1,1 SCK Mode 0,0 4 SI MSB in LSB in 5 6 10 7 2
SO
high impedance
DS22103A-page 40
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
FIGURE 2-8:
CS 8 SCK 9 2 Mode 1,1 Mode 0,0 12 13 SO MSB out 14 LSB out
SPI OUTPUT TIMING
SI
don't care
(c) 2008 Microchip Technology Inc.
DS22103A-page 41
MCP23018/MCP23S18
TABLE 2-5: SPI INTERFACE AC CHARACTERISTICS
Operating Conditions (unless otherwise indicated): 1.8V VDD 5.5V at -40C TA +125C. Sym FCLK TCSS TCSH TCSD TSU THD TR TF THI TLO TCLD TCLE TV THO TDIS Min -- 50 50 50 10 10 -- -- 45 45 50 50 -- 0 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 10 -- -- -- -- -- 2 2 -- -- -- -- 45 -- 100 Units MHz ns ns ns ns ns s s ns ns ns ns ns ns ns 1.8V - 5.5V 1.8V - 5.5V 1.8V - 5.5V 1.8V - 5.5V 1.8V - 5.5V Note 1 Note 1 1.8V - 5.5V 1.8V - 5.5V Conditions 1.8V - 5.5V SPI Interface AC Characteristics Param No. Characteristic Clock Frequency 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note 1: CS Setup Time CS Hold Time CS Disable Time Data Setup Time Data Hold Time CLK Rise Time CLK Fall Time Clock High Time Clock Low Time Clock Delay Time Clock Enable Time Output Valid from Clock Low Output Hold Time Output Disable Time
This parameter is characterized, not 100% tested.
FIGURE 2-9:
TYPICAL PERFORMANCE CURVE FOR SPI TV SPECIFICATION (PARAM #12)
TV vs VDD 40 35 30 25 20 15 10 5 0
T = +125C T = +85C
TV (ns)
T = -40C
T = +25C
1.5
2
2.5
3
3.5 VDD (V)
4
4.5
5
5.5
DS22103A-page 42
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
3.0
3.1
PACKAGING INFORMATION
Package Marking Information
24-Lead QFN Example
XXXXX XXXXXX XXXXXX YWWNNN
23018 e3 E/MJ^^ 0838 256
24-Lead SSOP (MCP23018 only)
Example:
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
MCP23018 e3 E/SS^^ 0838256
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2008 Microchip Technology Inc.
DS22103A-page 43
MCP23018/MCP23S18
Package Marking Information (Continued)
28-Lead SPDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example: MCP23018 e3 E/SP^^ 0838256
28-Lead SOIC (300 mil)
Example:
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
MCP23018 E/SO^^ e3 YYWW NNN
DS22103A-page 44
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
24-Lead Plastic Quad Flat, No Lead Package (MJ) - 4x4x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
(c) 2008 Microchip Technology Inc.
DS22103A-page 45
MCP23018/MCP23S18
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DS22103A-page 46
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
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(c) 2008 Microchip Technology Inc.
DS22103A-page 47
MCP23018/MCP23S18
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DS22103A-page 48
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
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E E1 NOTE 1 123 e b h h c
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L A1 L1
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(c) 2008 Microchip Technology Inc.
DS22103A-page 49
MCP23018/MCP23S18
NOTES:
DS22103A-page 50
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
APPENDIX A: REVISION HISTORY
Revision A (September 2008)
* Original Release of this Document.
(c) 2008 Microchip Technology Inc.
DS22103A-page 51
MCP23018/MCP23S18
NOTES:
DS22103A-page 52
(c) 2008 Microchip Technology Inc.
MCP23018/MCP23S18
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device
-
X
/XX Package
Examples: a) b) Extended Temp., 28LD SPDIP package. MCP23018-E/SO: Extended Temp., 28LD SOIC package. MCP23018T-E/SO: Tape and Reel, Extended Temp., 28LD SOIC package. MCP23018-E/SS: Extended Temp., 24LD SSOP package. MCP23018T-E/SS: Tape and Reel, Extended Temp., 24LD SSOP package. MCP23018-E/MJ: Extended Temp., 24LD QFN package. Extended Temp., 28LD SPDIP package. MCP23S18-E/SO: Extended Temp., 28LD SOIC package. MCP23S18T-E/SO: Tape and Reel, Extended Temp., 28LD SOIC package. MCP23S18T-E/MJ: Tape and Reel, Extended Temp., 24LD QFN package. MCP23S18-E/SP: MCP23018-E/SP:
Temperature Range
Device
MCP23018: MCP23018T: MCP23S18: MCP23S18T:
16-Bit I/O Expander w/ I2CTM Interface 16-Bit I/O Expander w/ I2C Interface (Tape and Reel) 16-Bit I/O Expander w/ SPI Interface 16-Bit I/O Expander w/ SPI Interface (Tape and Reel)
c)
d) e)
Temperature Range Package
E
= -40C to +125C (Extended) *
f)
a) MJ SP SO SS = Plastic Quad Flat, No Lead Package (4x4x0.9 mm Body), 24-Lead = Skinny Plastic DIP (300 mil Body), 28-Lead = Plastic SOIC (300 mil Body), 28-Lead = SSOP, (209 mil Body, 5.30 mm), 24-Lead b) c)
d)
(c) 2008 Microchip Technology Inc.
DS22103A-page 53
MCP23018/MCP23S18
NOTES:
DS22103A-page 54
(c) 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2008 Microchip Technology Inc.
DS22103A-page 55
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/02/08
DS22103A-page 56
(c) 2008 Microchip Technology Inc.

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